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| PSoCTM Mixed-Signal Array CY8C21234, CY8C21334, CY8C21434, CY8C21534, and CY8C21634 Final Data Sheet Features Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Low Power at High Speed 2.4V to 5.25V Operating Voltage Operating Voltages Down to 1.0V Using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Advanced Peripherals (PSoC Blocks) 4 Analog Type "E" PSoC Blocks Provide: - 2 Comparators with DAC Refs - Two 8-Bit 28 Channel ADCs 4 Digital PSoC Blocks Provide: - 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Full-Duplex UART, SPITM Master or Slave - Connectable to All GPIO Pins Complex Peripherals by Combining Blocks Flexible On-Chip Memory 8K Flash Program Storage 50,000 Erase/Write Cycles 512 Bytes SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Complete Development Tools Free Development Software (PSoCTM Designer) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator Internal Oscillator for Watchdog and Sleep Programmable Pin Configurations 25 mA Drive on All GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO Up to 8 Analog Inputs on GPIO Configurable Interrupt on All GPIO Versatile Analog Mux Common Internal Analog Bus Simultaneous Connection of IO Combinations Capacitive Sensing Application Capability Additional System Resources I2CTM Master, Slave and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Port 3 Port 2 Port 1 Port 0 PSoCTM Functional Overview The PSoCTM family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, as well as programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The PSoC architecture, as illustrated on the left, is comprised of four main areas: the Core, the System Resources, the Digital System, and the Analog System. Configurable global bus resources allow all the device resources to be combined into a complete custom system. Each CY8C21x34 PSoC device includes four digital blocks and four analog blocks. Depending on the PSoC package, up to 28 general purpose IO (GPIO) are also included. The GPIO provide access to the global digital and analog interconnects. PSoC CORE SystemBus Global Digital Interconnect SRAM 512 Bytes Interrupt Controller SROM Global Analog Interconnect Flash 8K Sleep and Watchdog CPU Core (M8C) Clock Sources (Includes IMO and ILO) DIGITAL SYSTEM Digital PSoC Block Array ANALOG SYSTEM Analog PSoC Block Array Analog Ref. The PSoC Core Digital Clocks POR and LVD I2C System Resets Sw itch Mode Pump Internal Voltage Ref. Analog Mux SYSTEM RESOURCES The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The December 17, 2004 (c) Cypress MicroSystems, Inc. 2004 -- Document No. 38-12025 Rev. *E 1 CY8C21x34 Final Data Sheet PSoCTM Overview CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such as digital clocks to increase the flexibility of the PSoC mixed-signal arrays, I2C functionality for implementing an I2C master, slave, MultiMaster, an internal voltage reference that provides an absolute value of 1.3V to a number of PSoC subsystems, a switch mode pump (SMP) that generates normal operating voltages off a single battery cell, and various system resets supported by the M8C. The Digital System is composed of an array of digital PSoC blocks, which can be configured into any number of digital peripherals. The digital blocks can be connected to the GPIO through a series of global buses that can route any signal to any pin. Freeing designs form the constraints of a fixed peripheral controller. The Analog System is composed of four analog PSoC blocks, supporting comparators and analog-to-digital conversion up to 8 bits in precision. Port 3 Port 2 Port 1 Port 0 DigitalClocks FromCore To System Bus To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row 0 DBB00 DBB01 DCB02 4 DCB03 4 Row Input Configuration Row Output Configuration 8 8 8 8 GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] The Digital System The Digital System is composed of 4 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below. Digital System Block Diagram The Analog System The Analog System is composed of 4 configurable blocks, allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are listed below. PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity SPI master and slave I2C slave and multi-master Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA Pseudo Random Sequence Generators (8 to 32 bit) Analog-to-digital converters (up to 2, with 8-bit resolution) Pin-to-pin comparator Single-ended comparators (up to 2) with absolute (1.3V) reference or 8-bit DAC reference 1.3V reference (as a System Resource) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled "PSoC Device Characteristics" on page 3. In most PSoC devices, analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks. The CY8C21x34 devices provide limited functionality Type "E" analog blocks. Each column contains one CT Type E block and one SC Type E block. Refer to the PSoC Mixed-Signal Array Technical Reference Manual for detailed information on the CY8C21x34's Type E analog blocks. December 17, 2004 Document No. 38-12025 Rev. *E 2 CY8C21x34 Final Data Sheet PSoCTM Overview Additional System Resources Array Input Configuration System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below. ACI0[1:0] All IO X X X X ACI1[1:0] Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. Versatile analog multiplexer system. ACOL1MUX AnalogMuxBus X Array ACE00 ASE10 ACE01 ASE11 Analog System Block Diagram PSoC Device Characteristics The Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted below. PSoC Device Characteristics Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital IO Digital Rows SRAM Size PSoC Part Number Flash Size CY8C29x66 Track pad, finger sensing. Chip-wide mux that allows analog input from any IO pin. Crosspoint connection between any IO pin combinations. CY8C24794 CY8C27x43 CY8C24x23 CY8C24x23A CY8C21x34 up to 64 up to 56 up to 44 up to 24 up to 24 up to 28 4 1 2 1 1 1 16 4 8 4 4 4 12 48 12 12 12 28 4 2 4 2 2 0 4 2 4 2 2 2 12 6 12 6 6 4a 2K 1K 256 Bytes 256 Bytes 256 Bytes 512 Bytes 32K 16K 16K 4K 4K 8K CY8C21x23 16 1 4 8 0 2 4a 256 Bytes 4K a. Limited analog functionality. December 17, 2004 Document No. 38-12025 Rev. *E 3 CY8C21x34 Final Data Sheet PSoCTM Overview Getting Started The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual, which can be found on http://www.cypress.com/psoc. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com. Development Tools The Cypress MicroSystems PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. PSoC TM Designer Graphical Designer Interface Context Sensitive Help Commands Results Technical Training Free PSoC technical training is available for beginners and is taught by a marketing or application engineer over the phone. PSoC training classes cover designing, debugging, advanced analog, as well as application-specific classes covering topics such as PSoC and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select Technical Training for more details. Importable Design Database Device Database Application Database Project Database User Modules Library Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants. PSoC TM Designer Core Engine PSoC Configuration Sheet Manufacturing Information File Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. Emulation Pod In-Circuit Emulator Device Programmer PSoC Designer Subsystems Application Notes A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are organized by part number. December 17, 2004 Document No. 38-12025 Rev. *E 4 CY8C21x34 Final Data Sheet PSoCTM Overview PSoC Designer Software Subsystems Device Editor The device editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator Design Browser The Design Browser allows users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports Cypress MicroSystems' PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. December 17, 2004 Document No. 38-12025 Rev. *E 5 CY8C21x34 Final Data Sheet PSoCTM Overview Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. Device Editor User Module Selection Placement and Parameter -ization Source Code Generator Generate Application A pplication Editor Project Manager Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager User Module and Source Code Development Flows The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. December 17, 2004 Document No. 38-12025 Rev. *E 6 CY8C21x34 Final Data Sheet PSoCTM Overview Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Acronym Description Table of Contents For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed-Signal Array Technical Reference Manual on http://www.cypress.com. This document encompasses and is organized into the following chapters and sections. 1. Pin Information ............................................................. 8 1.1 Pinouts ................................................................... 8 1.1.1 16-Pin Part Pinout ..................................... 8 1.1.2 20-Pin Part Pinout ..................................... 9 1.1.3 28-Pin Part Pinout ................................... 10 1.1.4 32-Pin Part Pinout ................................... 11 Register Reference ..................................................... 12 2.1 Register Conventions ........................................... 12 2.2 Register Mapping Tables ..................................... 12 Electrical Specifications ............................................ 15 3.1 Absolute Maximum Ratings ................................. 16 3.2 Operating Temperature ........................................ 16 3.3 DC Electrical Characteristics ................................ 16 3.3.1 DC Chip-Level Specifications ................... 16 3.3.2 DC General Purpose IO Specifications .... 17 3.3.3 DC Operational Amplifier Specifications ... 18 3.3.4 DC Switch Mode Pump Specifications ..... 19 3.3.5 DC Analog Mux Bus Specifications .......... 20 3.3.6 DC POR and LVD Specifications ............. 20 3.3.7 DC Programming Specifications ............... 21 3.4 AC Electrical Characteristics ................................ 22 3.4.1 AC Chip-Level Specifications ................... 22 3.4.2 AC General Purpose IO Specifications .... 24 3.4.3 AC Operational Amplifier Specifications ... 25 3.4.4 AC Analog Mux Bus Specifications .......... 25 3.4.5 AC Digital Block Specifications ................. 25 3.4.6 AC External Clock Specifications ............. 27 3.4.7 AC Programming Specifications ............... 28 3.4.8 AC I2C Specifications ............................... 28 Packaging Information ............................................... 30 4.1 Packaging Dimensions ......................................... 30 4.2 Thermal Impedances .......................................... 32 4.3 Solder Reflow Peak Temperature ........................ 33 Ordering Information .................................................. 34 5.1 Ordering Code Definitions .................................... 34 Sales and Service Information .................................. 35 6.1 Revision History ................................................... 35 6.2 Copyrights and Code Protection .......................... 35 AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoCTM PWM SC SLIMO SMP SRAM alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor slow IMO switch mode pump static random access memory 2. 3. 4. Units of Measure A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 15 lists all the abbreviations used to measure the PSoC devices. 5. 6. Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal. December 17, 2004 Document No. 38-12025 Rev. *E 7 1. Pin Information This chapter describes, lists, and illustrates the CY8C21x34 PSoC device pins and pinout configurations. 1.1 Pinouts The CY8C21x34 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 1.1.1 Pin No. 16-Pin Part Pinout Type Table 1-1. 16-Pin Part Pinout (SOIC) Digital Analog Name Description CY8C21234 16-Pin PSoC Device A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] SMP Vss M,I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IO IO IO IO I, M I, M I, M I, M Power Power P0[7] P0[5] P0[3] P0[1] SMP Vss Analog column mux input. Analog column mux input. Analog column mux input, integrating input. Analog column mux input, integrating input. Switch Mode Pump (SMP) connection to required external components. Ground connection. I2C Serial Clock (SCL). Ground connection. I2C Serial Data (SDA). Optional External Clock Input (EXTCLK). Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. 1 2 3 4 5 6 7 8 SOIC 16 15 14 13 12 11 10 9 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P1[4], EXTCLK,M P1[2],M P1[0], I2C SDA, M IO Power IO IO IO IO IO IO IO M M M M I, M I, M I, M I, M Power P1[1] Vss P1[0] P1[2] P1[4] P0[0] P0[2] P0[4] P0[6] Vdd LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. December 17, 2004 Document No. 38-12025 Rev. *E 8 CY8C21x34 Final Data Sheet 1. Pin Information 1.1.2 Pin No. 20-Pin Part Pinout Type Table 1-2. 20-Pin Part Pinout (SSOP) Digital Analog Name Description CY8C21334 20-Pin PSoC Device A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] Vss M,I2C SCL, P1[7] M,I2C SDA, P1[5] M,P1[3] M,I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IO IO IO IO I, M I, M I, M I, M Power P0[7] P0[5] P0[3] P0[1] Vss Analog column mux input. Analog column mux input. Analog column mux input, integrating input. Analog column mux input, integrating input. Ground connection. I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL). Ground connection. I2C Serial Data (SDA). Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. IO IO IO IO Power IO IO IO IO Input IO IO IO IO M M M M M M M M P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES 1 2 3 4 5 6 7 8 9 10 SSOP 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M XRES P1[6],M P1[4], EXTCLK,M P1[2],M P1[0],I2C SDA, M I, M I, M I, M I, M Power P0[0] P0[2] P0[4] P0[6] Vdd LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. December 17, 2004 Document No. 38-12025 Rev. *E 9 CY8C21x34 Final Data Sheet 1. Pin Information 1.1.3 Pin No. 28-Pin Part Pinout Type Table 1-3. 28-Pin Part Pinout (SSOP) Digital Analog Name Description CY8C21534 28-Pin PSoC Device A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] M,P2[7] M,P2[5] M, P2[3] M, P2[1] Vss M,I2C SCL, P1[7] M,I2C SDA, P1[5] M,P1[3] M,I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IO IO IO IO IO IO IO IO Power IO IO IO IO Power IO IO IO IO Input IO IO IO IO IO IO IO IO Power I, M I, M I, M I, M M M I, M I, M M M M M M M M M P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES Analog column mux input. Analog column mux input and column output. Analog column mux input and column output, integrating input. Analog column mux input, integrating input. Direct switched capacitor block input. Direct switched capacitor block input. Ground connection. I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL). Ground connection. I2C Serial Data (SDA). Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6],M P2[4],M P2[2],M P2[0],M XRES P1[6],M P1[4],EXTCLK,M P1[2],M P1[0],I2C SDA, M I, M I, M M M I, M I, M I, M I, M P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Analog column mux input. Analog column mux input. Analog column mux input Analog column mux input. Supply voltage. LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input. December 17, 2004 Document No. 38-12025 Rev. *E 10 CY8C21x34 Final Data Sheet 1. Pin Information 1.1.4 Pin No. 32-Pin Part Pinout Type Table 1-4. 32-Pin Part Pinout (MLF*) Digital Analog Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M 32 31 30 29 28 27 26 25 A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] M, P3[3] M, P3[1] M, I2C SCL, P1[7] 1 2 3 4 5 6 7 8 Name Description CY8C21434 32-Pin PSoC Device 1 2 3 4 5 6 6 IO IO IO IO IO IO I, M M M M M M Power P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] SMP Analog column mux input, integrating input. In CY8C21434 part. Switch Mode Pump (SMP) connection to required external components in CY8C21634 part. In CY8C21434 part. Ground connection in CY8C21634 part. I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL). Ground connection. I2C Serial Data (SDA). Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. MLF (Top View ) 7 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IO Power IO IO IO IO Power IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO IO IO IO M M M M M M M M M P3[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES CY8C21634 32-Pin PSoC Device Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] SMP Vss M, I2C SCL, P1[7] 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 M M M M M M I, M I, M I, M I, M Power I, M I, M I, M Power P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input. Analog column mux input, integrating input. Ground connection. M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] 9 10 11 12 13 14 15 16 MLF (Top View ) LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * The MLF package has a center pad that must be connected to ground (Vss). December 17, 2004 Document No. 38-12025 Rev. *E M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES 11 2. Register Reference This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, reference the PSoCTM Mixed-Signal Array Technical Reference Manual. 2.1 Register Conventions 2.2 Register Mapping Tables The register conventions specific to this section are listed in the following table. Convention Description R W L C # Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are Reserved and should not be accessed. December 17, 2004 Document No. 38-12025 Rev. *E 12 CY8C21x34 Final Data Sheet 2. Register Reference Register Map 0 Table: User Space Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C RW 4C 0D RW 4D 0E RW 4E 0F RW 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00DR0 20 # AMX_IN 60 DBB00DR1 21 W AMUXCFG 61 DBB00DR2 22 RW PWM_CR 62 DBB00CR0 23 # 63 DBB01DR0 24 # CMP_CR0 64 DBB01DR1 25 W 65 DBB01DR2 26 RW CMP_CR1 66 DBB01CR0 27 # 67 DCB02DR0 28 # ADC0_CR 68 DCB02DR1 29 W ADC1_CR 69 DCB02DR2 2A RW 6A DCB02CR0 2B # 6B DCB03DR0 2C # TMP0_DR 6C DCB03DR1 2D W TMP1_DR 6D DCB03DR2 2E RW TMP2_DR 6E DCB03CR0 2F # TMP3_DR 6F 30 70 31 71 32 ACE00CR1 72 33 ACE00CR2 73 34 74 35 75 36 ACE01CR1 76 37 ACE01CR2 77 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed. RW RW RW # RW # # RW RW RW RW RW RW RW RW 80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. ASE10CR0 RW RW CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_CR0 DEC_CR1 RW RW RW RW RW RW RW CPU_F DAC_D CPU_SCR1 CPU_SCR0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW # RW # RW RW RW RW RW RW RC W RW RW RL RW # # December 17, 2004 Document No. 38-12025 Rev. *E 13 CY8C21x34 Final Data Sheet 2. Register Reference Register Map 1 Table: Configuration Space Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C RW 4C 0D RW 4D 0E RW 4E 0F RW 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00FN 20 RW CLK_CR0 60 DBB00IN 21 RW CLK_CR1 61 DBB00OU 22 RW ABF_CR0 62 23 AMD_CR0 63 DBB01FN 24 RW CMP_GO_EN 64 DBB01IN 25 RW 65 DBB01OU 26 RW AMD_CR1 66 27 ALT_CR0 67 DCB02FN 28 RW 68 DCB02IN 29 RW 69 DCB02OU 2A RW 6A 2B CLK_CR3 6B DCB03FN 2C RW TMP0_DR 6C DCB03IN 2D RW TMP1_DR 6D DCB03OU 2E RW TMP2_DR 6E 2F TMP3_DR 6F 30 70 31 71 32 ACE00CR1 72 33 ACE00CR2 73 34 74 35 75 36 ACE01CR1 76 37 ACE01CR2 77 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed. PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 ASE10CR0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW RW RW C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF GDI_O_IN D0 GDI_E_IN D1 GDI_O_OU D2 GDI_E_OU D3 D4 D5 D6 D7 MUX_CR0 D8 MUX_CR1 D9 MUX_CR2 DA MUX_CR3 DB DC OSC_GO_EN DD OSC_CR4 DE OSC_CR3 DF OSC_CR0 E0 OSC_CR1 E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 ADC0_TR E5 ADC1_TR E6 E7 IMO_TR E8 ILO_TR E9 BDG_TR EA ECO_TR EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FLS_PR1 FA FB FC DAC_CR FD CPU_SCR1 FE CPU_SCR0 FF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW W W RW W RL RW RW # # December 17, 2004 Document No. 38-12025 Rev. *E 14 3. Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC as specified, except where noted. Refer to Table 3-14 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. 5.25 5.25 SLIMO Mode=1 4.75 Vdd Voltage 4.75 Vdd Voltage SLIMO Mode = 0 SLIMO Mode=0 lid ng Va rati n e io Op Reg 3.60 3.00 2.40 93 kHz 3 MHz 12 MHz CPU Frequency 24 MHz 3.00 2.40 93 kHz SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=1 6 MHz 12 MHz 24 MHz IMO Frequency Figure 3-1a. Voltage versus CPU Frequency Figure 3-1b. IMO Frequency Trim Options The following table lists the units of measure that are used in this chapter. Table 3-1: Units of Measure Symbol oC Unit of Measure Symbol W Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms mA ms mV nA ns nV pA pF pp ppm ps sps V December 17, 2004 Document No. 38-12025 Rev. *E 15 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.1 Symbol TSTG TA Vdd VIO VIOZ IMIO ESD LU Absolute Maximum Ratings Description Storage Temperature Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch-up Current Min -55 -40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 - - - - - - - - - Typ Max +100 +85 +6.0 Units oC oC Table 3-2. Absolute Maximum Ratings Notes Higher storage temperatures will reduce data retention time. V Vdd + 0.5 V Vdd + 0.5 V +50 - 200 mA V mA Human Body Model ESD. 3.2 Symbol TA TJ Operating Temperature Description Ambient Temperature Junction Temperature Min -40 -40 - - Typ Max +85 +100 Units oC oC Table 3-3. Operating Temperature Notes The temperature rise from ambient to junction is package specific. See "Thermal Impedances" on page 32. The user must limit the power consumption to comply with this requirement. 3.3 3.3.1 DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-4. DC Chip-Level Specifications Symbol Vdd IDD Supply Voltage Supply Current, IMO = 24 MHz Description Min 2.40 - - 3 Typ Max 5.25 4 V mA Units Notes See table titled "DC POR and LVD Specifications" on page 20. Conditions are Vdd = 5.0V, TA = 25oC, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. Conditions are Vdd = 2.55V, TA = 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. Vdd = 2.55V, 0oC TA 40oC. Vdd = 3.3V, -40oC TA 85oC. Trimmed for appropriate Vdd. Vdd = 3.0V to 5.25V. Trimmed for appropriate Vdd. Vdd = 2.4V to 3.0V. IDD3 Supply Current, IMO = 6 MHz using SLIMO mode. - 1.2 2 mA IDD27 Supply Current, IMO = 6 MHz using SLIMO mode. - 1.1 1.5 mA ISB27 ISB VREF VREF27 AGND Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Mid temperature range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Reference Voltage (Bandgap) Reference Voltage (Bandgap) Analog Ground - - 1.28 1.16 VREF - 0.003 2.5 2.8 1.30 1.30 VREF 3. 5 1.32 1.33 VREF + 0.003 A A V V V December 17, 2004 Document No. 38-12025 Rev. *E 16 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.3.2 DC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-5. 5V and 3.3V DC GPIO Specifications Symbol RPU RPD VOH Pull-up Resistor Pull-down Resistor High Output Level Description 4 4 Vdd - 1.0 Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes VOL Low Output Level - - 0.75 V VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - 2.1 - - - - - - 60 1 3.5 3.5 0.8 - - 10 10 V V mV nA pF pF Table 3-6. 2.7V DC GPIO Specifications Symbol RPU RPD VOH Pull-up Resistor Pull-down Resistor High Output Level Description 4 4 Vdd - 0.4 Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 2.5 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16 mA maximum, 50 mA Typ combined IOH budget). IOL = 10 mA, Vdd = 2.4 to 3.0V (90 mA maximum combined IOL budget). Vdd = 2.4 to 3.0. Vdd = 2.4 to 3.0. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes VOL VIL VIH VH IIL CIN COUT Low Output Level Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - - 2.0 - - - - - - - 90 1 3.5 3.5 0.75 0.75 - - - 10 10 V V V mV nA pF pF December 17, 2004 Document No. 38-12025 Rev. *E 17 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.3.3 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-7. 5V DC Operational Amplifier Specifications Symbol VOSOA TCVOSOA IEBOA CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current - - - - 0.0 - - Min 10 200 4.5 - 80 10 Typ 2.5 15 - - 9.5 Vdd - 1 - 30 Max Units mV V/oC Notes pA pF V dB A Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Table 3-8. 3.3V DC Operational Amplifier Specifications Symbol VOSOA TCVOSOA IEBOA CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current - - - - 0 - - Min Typ 2.5 10 200 4.5 - 80 10 Max 15 - - 9.5 Vdd - 1 - 30 Units mV V/oC Notes pA pF V dB A Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Table 3-9. 2.7V DC Operational Amplifier Specifications Symbol VOSOA TCVOSOA IEBOA CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current - - - - 0 - - Min Typ 2.5 10 200 4.5 - 80 10 Max 15 - - 9.5 Vdd - 1 - 30 Units mV V/oC Notes pA pF V dB A Gross tested to 1 A. Package and pin dependent. Temp = 25oC. December 17, 2004 Document No. 38-12025 Rev. *E 18 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.3.4 DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-10. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP5V VPUMP3V VPUMP2V IPUMP Description 5V Output Voltage from Pump 3.3V Output Voltage from Pump 2.6V Output Voltage from Pump Available Output Current VBAT = 1.8V, VPUMP = 5.0V VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.3V, VPUMP = 2.55V VBAT5V VBAT3V VBAT2V VBATSTART VPUMP_Line Min 4.75 3.00 2.45 Typ 5.0 3.25 2.55 Max 5.25 3.60 2.80 V V V Units Notes Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 2.55V. Configuration of footnote.a SMP trip voltage is set to 5.0V. SMP trip voltage is set to 3.25V. SMP trip voltage is set to 2.55V. Configuration of footnote.a SMP trip voltage is set to 5.0V. Configuration of footnote.a SMP trip voltage is set to 3.25V. Configuration of footnote.a SMP trip voltage is set to 2.55V. Configuration of footnote.a 0oC TA 100. 1.25V at TA = -40oC. Configuration of footnote.a VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 312 on page 20. Configuration of footnote.a VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 312 on page 20. Configuration of footnote.a Load is 5 mA. Configuration of footnote.a Load is 5 mA. SMP trip voltage is set to 3.25V. For I load = 1mA, VPUMP = 2.55V, VBAT = 1.3V, 10 uH inductor, 1 uF capacitor, and Schottky diode. 5 8 8 1.8 1.0 1.0 1.2 - - - - - - - - 5 - - - 5.0 3.3 2.8 - - mA mA mA V V V V %VO Input Voltage Range from Battery Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over Vi range) VPUMP_Load Load Regulation - 5 - %VO VPUMP_Ripple Output Voltage Ripple (depends on cap/load) Efficiency Efficiency - 35 35 100 50 80 - - - mVpp % % E3 E2 FPUMP DCPUMP Switching Frequency Switching Duty Cycle - - 1.3 50 - - MHz % a. L1 = 2 H inductor, C1 = 10 F capacitor, D1 = Schottky diode. See Figure 3-2. D1 Vdd V PUMP L1 V BAT + SMP Battery PSoCTM V ss C1 Figure 3-2. Basic Switch Mode Pump Circuit December 17, 2004 Document No. 38-12025 Rev. *E 19 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.3.5 DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-11. DC Analog Mux Bus Specifications Symbol RSW RVDD Description Switch Resistance to Common Analog Bus Resistance of Initialization Switch to Vdd - - Min - - Typ Max 400 800 800 Units Vdd 2.7V 2.4V Vdd 2.7V Notes 3.3.6 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-12. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.62c 3.09 3.16 3.32d 4.74 4.83 4.92 5.12 V V V V V V V V 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51a 2.99b 3.09 3.20 4.55 4.75 4.83 4.95 V V V V V V V V - Description Vdd Value for PPOR Trip 2.36 2.82 4.55 2.40 2.95 4.70 V V V Min Typ Max Units Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. a. b. c. d. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. Always greater than 50 mV above VLVD0. Always greater than 50 mV above VLVD3. December 17, 2004 Document No. 38-12025 Rev. *E 20 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.3.7 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-13. DC Programming Specifications Symbol VddIWRITE IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Voltage for Flash Write Operations Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total)a Flash Data Retention - - 2.2 - - - Vdd - 1.0 50,000 1,800,000 10 Min 2.70 - 5 - - - - - - - - - Typ - 25 0.8 - 0.2 1.5 Max V mA V V mA mA Driving internal pull-down resistor. Driving internal pull-down resistor. Units Notes Vss + 0.75 V Vdd - - - V - - Years Erase/write cycles per block. Erase/write cycles. a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. December 17, 2004 Document No. 38-12025 Rev. *E 21 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.4 3.4.1 AC Electrical Characteristics AC Chip-Level Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-14. 5V and 3.3V AC Chip-Level Specifications Symbol FIMO24 Description Internal Main Oscillator Frequency for 24 MHz Min 23.4 24 Typ Max 24.6a,b,c Units MHz Notes Trimmed for 5V or 3.3V operation using factory trim values. See Figure 3-1b on page 15. SLIMO mode = 0. Trimmed for 5V or 3.3V operation using factory trim values. See Figure 3-1b on page 15. SLIMO mode = 1. 24 MHz only for SLIMO mode = 0. Refer to the AC Digital Block Specifications below. FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35a,b,c MHz FCPU1 FCPU2 FBLK5 FBLK33 F32K1 Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency0(5V Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. Supply Ramp Time 0.93 0.93 0 0 15 - 10 40 - 46.8 - - 0 24 12 48 24 32 100 - 50 50 48.0 600 - - 24.6a,b 12.3b,c 49.2a,b,d 24.6b,d 64 200 - 60 - 49.2a,c 12.3 - MHz MHz MHz MHz kHz ns s % kHz MHz ps MHz s Trimmed. Utilizing factory trim values. a. b. c. d. 4.75V < Vdd < 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. See the individual user module data sheets for information on maximum frequencies for user modules. Table 3-15. 2.7V AC Chip-Level Specifications Symbol FIMO12 Description Internal Main Oscillator Frequency for 12 MHz Min 11.5 Typ 120 Max 12.7a,b,c Units MHz Notes Trimmed for 2.7V operation using factory trim values. See Figure 3-1b on page 15. SLIMO mode = 1. Trimmed for 2.7V operation using factory trim values. See Figure 3-1b on page 15. SLIMO mode = 1. 24 MHz only for SLIMO mode = 0. Refer to the AC Digital Block Specifications below. FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35a,b,c MHz FCPU1 FBLK27 F32K1 Jitter32k TXRST FMAX TRAMP CPU Frequency (2.7V Nominal) Digital PSoC Block Frequency (2.7V Nominal) Internal Low Speed Oscillator Frequency 32 kHz Period Jitter External Reset Pulse Width Maximum frequency of signal on row input or row output. Supply Ramp Time 0.093 0 8 - 10 - 0 3 12 32 150 - - - 3.15a,b 12.5a,b,c 96 200 - 12.3 - MHz MHz kHz ns s MHz s a. 2.4V < Vdd < 3.0V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on maximum frequency for user modules. December 17, 2004 Document No. 38-12025 Rev. *E 22 CY8C21x34 Final Data Sheet 3. Electrical Specifications Jitter24M1 F 24M Figure 3-3. 24 MHz Period Jitter (IMO) Timing Diagram Jitter32k F 32K1 Figure 3-4. 32 kHz Period Jitter (ILO) Timing Diagram December 17, 2004 Document No. 38-12025 Rev. *E 23 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.4.2 AC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-16. 5V and 3.3V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 3 2 7 7 Min - - - 27 22 Typ 12 18 18 - - Max Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Table 3-17. 2.7V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 6 6 18 18 Min - - - 40 40 Typ 3 50 50 120 120 Max Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Figure 3-5. GPIO Timing Diagram December 17, 2004 Document No. 38-12025 Rev. *E 24 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.4.3 AC Operational Amplifier Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-18. AC Operational Amplifier Specifications Symbol TCOMP Description Comparator Mode Response Time, 50 mV Overdrive Min Typ Max 100 200 Units ns ns Vdd 3.0V. 2.4V < Vcc < 3.0V. Notes 3.4.4 AC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-19. AC Analog Mux Bus Specifications Symbol FSW Switch Rate Description - Min - Typ Max 3.17 Units MHz Notes 3.4.5 AC Digital Block Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-20. 5V and 3.3V AC Digital Block Specifications Function All Functions Timer Description Maximum Block Clocking Frequency (> 4.75V) Maximum Block Clocking Frequency (< 4.75V) Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With or Without Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency 20 50 50 - - - - - 50 - - - - - - - - - - - - - - - - 49.2 49.2 24.6 8.2 4.1 - 24.6 24.6 ns ns ns MHz MHz MHz MHz MHz ns MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 4.1 MHz due to 2 x over clocking. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 50a - - 50 - - - - - - - - Min Typ Max 49.2 24.6 - 49.2 24.6 - 49.2 24.6 Units MHz MHz ns MHz MHz ns MHz MHz 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Notes 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V. a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). December 17, 2004 Document No. 38-12025 Rev. *E 25 CY8C21x34 Final Data Sheet 3. Electrical Specifications Table 3-21. 2.7V AC Digital Block Specifications Function All Functions Timer Description Maximum Block Clocking Frequency Capture Pulse Width Maximum Frequency, With or Without Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency 20 100 100 - - - - - 100 - - - - - - - - - - - - - - - - 12.7 12.7 12.7 6.35 4.1 - 12.7 12.7 ns ns ns MHz MHz MHz MHz MHz ns MHz MHz Maximum data rate at 1.59 MHz due to 8 x over clocking. Maximum data rate at 1.59 MHz due to 8 x over clocking. Maximum data rate at 3.17 MHz due to 2 x over clocking. 100a - 100 - - - - - - - Min Typ Max 12.7 - 12.7 - 12.7 12.7 Units MHz ns MHz ns MHz MHz 2.4V < Vdd < 3.0V. Notes a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). December 17, 2004 Document No. 38-12025 Rev. *E 26 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.4.6 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-22. 5V AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0.093 20.6 20.6 150 - - - - Typ Max 24.6 5300 - - Units MHz ns ns s Notes Table 3-23. 3.3V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.093 - Typ Max 12.3 Units MHz Notes Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.186 - 24.6 MHz - - - High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 41.7 41.7 150 - - - 5300 - - ns ns s Table 3-24. 2.7V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.093 - Typ Max 3.080 Units MHz Notes Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.186 - 6.35 MHz - - - High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 160 160 150 - - - 5300 - - ns ns s December 17, 2004 Document No. 38-12025 Rev. *E 27 CY8C21x34 Final Data Sheet 3. Electrical Specifications 3.4.7 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-25. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Description 1 1 40 40 0 - - - - - Min - - - - - 15 30 - - - Typ 20 20 - - 8 - - 45 50 70 Max Units ns ns ns ns MHz ms ms ns ns ns 3.6 < Vdd 3.0 Vdd 3.6 2.4 Vdd 3.0 Notes 3.4.8 AC I2C Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-26. AC Characteristics of the I2C SDA and SCL Pins for Vdd 3.0V Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Pulse Width of spikes are suppressed by the input filter. 0 4.0 4.7 4.0 4.7 0 250 4.0 - Min - - - - - - - - - Max 100 0 0.6 1.3 0.6 0.6 0 100a 0.6 1.3 0 Fast Mode Min - - - - - - - - 50 Max 400 Units kHz s s s s s Notes ns s s Bus Free Time Between a STOP and START Condition 4.7 ns a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Table 3-27. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time 0 4.0 4.7 4.0 4.7 0 Min - - - - - Max 100 - - - - - - Fast Mode Min - - - - - - Max Units kHz s s s s s Notes December 17, 2004 Document No. 38-12025 Rev. *E 28 CY8C21x34 Final Data Sheet 3. Electrical Specifications Table 3-27. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) (continued) Standard Mode Symbol TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Data Set-up Time Set-up Time for STOP Condition Pulse Width of spikes are suppressed by the input filter. Description Min 250 4.0 - - - - - Max - - - - Fast Mode Min - - - - Max Units ns s s Notes Bus Free Time Between a STOP and START Condition 4.7 ns SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Figure 3-6. Definition for Timing for Fast/Standard Mode on the I2C Bus December 17, 2004 Document No. 38-12025 Rev. *E 29 4. Packaging Information This chapter illustrates the packaging specifications for the CY8C21x34 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/support/link.cfm?mr=poddim. 4.1 Packaging Dimensions PIN 1 ID 8 1 * 0.291[7.391] 0.299[7.594] * 0.394[10.007] 0.419[10.642] DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-119 MIN. MAX. 9 16 0.026[0.660] 0.032[0.812] PART # S16.3 STANDARD PKG. SZ16.3 LEAD FREE PKG. 0.397[10.083] 0.413[10.490] SEATING PLANE 0.092[2.336] 0.105[2.667] 0.004[0.101] 0.050[1.270] TYP. 0.013[0.330] 0.019[0.482] 0.004[0.101] 0.0118[0.299] * 0.015[0.381] 0.050[1.270] * 0.0091[0.231] 0.0125[0.317] 51-85022 *B Figure 4-1. 16-Lead (150-Mil) SOIC December 17, 2004 Document No. 38-12025 Rev. *E 30 CY8C21x34 Final Data Sheet 4. Packaging Information 51-85077 *C Figure 4-2. 20-Lead (210-MIL) SSOP 51-85079 - *C Figure 4-3. 28-Lead (210-Mil) SSOP December 17, 2004 Document No. 38-12025 Rev. *E 31 CY8C21x34 Final Data Sheet 4. Packaging Information 51-85188 ** Figure 4-4. 32-Lead (5x5 mm) MLF 4.2 Thermal Impedances Package 16 SOIC 20 SSOP 28 SSOP 32 MLF Typical o Table 4-1. Thermal Impedances per Package JA * 96 C/W 95 oC/W 101 oC/W 22 oC/W * TJ = TA + Power x JA December 17, 2004 Document No. 38-12025 Rev. *E 32 CY8C21x34 Final Data Sheet 4. Packaging Information 4.3 Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 4-2. Solder Reflow Peak Temperature Package 16 SOIC 20 SSOP 28 SSOP 32 MLF Minimum Peak Temperature* 220oC 240oC 240oC 220oC Maximum Peak Temperature 260oC 260oC 260oC 260oC *Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC with Sn-Pb or 245+/-5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. December 17, 2004 Document No. 38-12025 Rev. *E 33 5. Ordering Information The following table lists the CY8C21x34 PSoC device's key package features and ordering codes. CY8C21x34 PSoC Device Key Features and Ordering Information Switch Mode Pump Temperature Range XRES Pin No No Yes Yes Yes Yes Yes Yes Yes Yes Digital IO Pins Ordering Code Package Analog Outputs 0 0 0 0 0 0 0 0 0 0 Inputs a Flash (Bytes) SRAM (Bytes) Analog Blocks Analog Digital Blocks 16 Pin (150-Mil) SOIC 16 Pin (150-Mil) SOIC (Tape and Reel) 20 Pin (300-Mil) SSOP 20 Pin (300-Mil) SSOP (Tape and Reel) 28 Pin (210-Mil) SSOP 28 Pin (210-Mil) SSOP (Tape and Reel) 32 Pin (5x5) MLF b 32 Pin (5x5) MLF (Tape and Reel) b CY8C21234-24SXI CY8C21234-24SXIT CY8C21334-24PVXI CY8C21334-24PVXIT CY8C21534-24PVXI CY8C21534-24PVXIT CY8C21434-24LFXI CY8C21434-24LFXIT CY8C21634-24LFXI CY8C21634-24LFXIT 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 512 512 512 512 512 512 512 512 512 512 Yes Yes No No No No No No Yes Yes -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 12 12 16 16 24 24 28 28 26 26 12a 12a 16a 16a 24a 24a 28a 28a 26a 26a 32 Pin (5x5) MLF b 32 Pin (5x5) MLF b (Tape and Reel) a. All Digital IO Pins also connect to the common analog mux. b. Refer to the "32-Pin Part Pinout" on page 11 for pin differences. 5.1 Ordering Code Definitions CY 8 C 21 xxx-24xx Package Type: PX = PDIP Pb-Free SX = SOIC Pb-Free PVX = SSOP Pb-Free LFX = MLF Pb-Free AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress MicroSystems Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended December 17, 2004 Document No. 38-12025 Rev. *E 34 6. Sales and Service Information To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to the section titled "Getting Started" on page 4 in this document. Cypress MicroSystems 2700 162nd Street SW Building D Lynnwood, WA 98037 Phone: Facsimile: Web Sites: 800.669.0557 425.787.4641 Company Information - http://www.cypress.com Sales - http://www.cypress.com/aboutus/sales_locations.cfm Technical Support - http://www.cypress.com/support/login.cfm 6.1 Revision History Document Title: CY8C21234, CY8C21334, CY8C21434, CY8C21534, and CY8C21634 PSoC Mixed-Signal Array Final Data Sheet Document Number: 38-12025 Origin of Revision ECN # Issue Date Description of Change Change ** *A 227340 235992 05/19/2004 See ECN HMT SFV New silicon and document (Revision **). Updated Overview and Electrical Spec. chapters, along with revisions to the 24-pin pinout part. Revised the register mapping tables. Added a SSOP 28-pin part. Changed title to include all part #s. Changed 28-pin SSOP from CY8C21434 to CY8C21534. Changed pin 9 on the 28-pin SSOP from SMP pin to Vss pin. Added SMP block to architecture diagram. Update Electrical Specifications. Added another 32-pin MLF part: CY8C21634. Verify data sheet standards from SFV memo. Add Analog Input Mux to applicable pin outs. Update PSoC Characteristics table. Update diagrams and specs. Final. Update 2.7V DC GPIO spec. Add Reflow Peak Temp. table. DC Chip-Level Specification changes. Update links to new CY.com Portal. *B 248572 277832 285293 301739 See ECN See ECN See ECN See ECN SFV HMT HMT HMT *C *D *E Distribution: External/Public Posting: None 6.2 Copyrights and Code Protection (c) Cypress MicroSystems, Inc. 2004. All rights reserved. PSoCTM, PSoC DesignerTM, and Programmable System-on-ChipTM are trademarks of Cypress MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress MicroSystems. Note the following details of the Flash code protection features on Cypress MicroSystems devices. Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress MicroSystems, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress MicroSystems nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress MicroSystems are committed to continuously improving the code protection features of our products. December 17, 2004 (c) Cypress MicroSystems, Inc. 2004 -- Document No. 38-12025 Rev. *E 35 |
Price & Availability of CY8C21234-24SXI
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